Dynamic load balancing and resource allocation for vertex, geometry, and pixel shaders
Common instruction set and texture unit access supported for all types of shaders
Dedicated branch execution units and texture address processors
• 128-bit floating point precision for all operations
• Command processor for reduced CPU overhead
• Shader instruction and constant caches
• Up to 160 texture fetches per clock cycle
• Up to 128 textures per pixel
• Fully associative multi-level texture cache design
• DXTC and 3Dc+ texture compression
• High resolution texture support (up to 8192 x 8192)
• Fully associative texture Z/stencil cache designs
• Double-sided hierarchical Z/stencil buffer
• Early Z test, Re-Z, Z Range optimization, and Fast Z Clear
• Lossless Z & stencil compression (up to 128:1)
• Lossless color compression (up to 8:1)
• 8 render targets (MRTs) with anti-aliasing support
• Accelerated physics processin
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Nanotec Digital for R1 599.00
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